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K40P121M100SF2 k40 sub-family data sheet supports the following: mk40n512vmc100 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? performance C up to 100 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz ? memories and memory interfaces C up to 512 kb program flash memory on non- flexmemory devices C up to 128 kb ram C serial programming interface (ezport) ? clocks C 3 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C 10 low-power modes to provide power optimization based on application requirements C memory protection unit with multi-master protection C 16-channel dma controller, supporting up to 64 request sources C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C 128-bit unique identification (id) number per chip ? human-machine interface C segment lcd controller supporting up to 40 frontplanes and 8 backplanes, or 44 frontplanes and 4 backplanes C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C two 16-bit sar adcs C programmable gain amplifier (up to x64) integrated into each adc C two 12-bit dacs C three analog comparators (cmp) containing a 6-bit dac and programmable reference input C voltage reference ? timers C programmable delay block C eight-channel motor control/general purpose/pwm timer C two 2-channel quadrature decoder/general purpose timers C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock ? communication interfaces C usb full-/low-speed on-the-go controller with on- chip transceiver C two controller area network (can) modules C three spi modules C two i2c modules C five uart modules C secure digital host controller (sdhc) C i2s module freescale semiconductor document number: K40P121M100SF2 data sheet: product preview rev. 4, 3/2011 this document contains information on a product under development. freescale reserves the right to change or discontinue this product without notice. ? 2010C2011 freescale semiconductor, inc. preliminary
table of contents 1 ordering parts ........................................................................... 3 1.1 determining valid orderable parts...................................... 3 2 part identification ...................................................................... 3 2.1 description......................................................................... 3 2.2 format ............................................................................... 3 2.3 fields ................................................................................. 3 2.4 example ............................................................................ 4 3 terminology and guidelines ...................................................... 4 3.1 definition: operating requirement...................................... 4 3.2 definition: operating behavior ........................................... 5 3.3 definition: attribute ............................................................ 5 3.4 definition: rating ............................................................... 6 3.5 result of exceeding a rating .............................................. 6 3.6 relationship between ratings and operating requirements...................................................................... 6 3.7 guidelines for ratings and operating requirements............ 7 3.8 definition: typical value..................................................... 7 3.9 typical value conditions .................................................... 8 4 ratings ...................................................................................... 8 4.1 thermal handling ratings ................................................... 9 4.2 moisture handling ratings .................................................. 9 4.3 esd handling ratings ......................................................... 9 4.4 voltage and current operating ratings ............................... 9 5 general ..................................................................................... 10 5.1 nonswitching electrical specifications ............................... 10 5.1.1 voltage and current operating requirements ...... 10 5.1.2 lvd and por operating requirements ............... 11 5.1.3 voltage and current operating behaviors ............ 12 5.1.4 power mode transition operating behaviors ....... 12 5.1.5 power consumption operating behaviors............ 13 5.1.6 emc radiated emissions operating behaviors .... 16 5.1.7 designing with radiated emissions in mind ......... 17 5.1.8 capacitance attributes ........................................ 17 5.2 switching specifications..................................................... 17 5.2.1 device clock specifications ................................. 17 5.2.2 general switching specifications......................... 18 5.3 thermal specifications ....................................................... 18 5.3.1 thermal operating requirements......................... 18 5.3.2 thermal attributes ............................................... 19 6 peripheral operating requirements and behaviors .................... 19 6.1 core modules .................................................................... 19 6.1.1 debug trace timing specifications ....................... 19 6.1.2 jtag electricals.................................................. 20 6.2 system modules ................................................................ 23 6.3 clock modules ................................................................... 23 6.3.1 mcg specifications ............................................. 23 6.3.2 oscillator electrical specifications ....................... 26 6.3.3 32khz oscillator electrical characteristics ......... 28 6.4 memories and memory interfaces ..................................... 28 6.4.1 flash (ftfl) electrical specifications ................. 29 6.4.2 ezport switching specifications ......................... 30 6.5 security and integrity modules .......................................... 31 6.6 analog ............................................................................... 31 6.6.1 adc electrical specifications .............................. 31 6.6.2 cmp and 6-bit dac electrical specifications ...... 38 6.6.3 12-bit dac electrical characteristics ................... 41 6.6.4 voltage reference electrical specifications.......... 44 6.7 timers................................................................................ 45 6.8 communication interfaces ................................................. 45 6.8.1 usb electrical specifications............................... 46 6.8.2 usb dcd electrical specifications ...................... 46 6.8.3 usb vreg electrical specifications ................... 46 6.8.4 can switching specifications .............................. 47 6.8.5 dspi switching specifications (low-speed mode).................................................................. 47 6.8.6 dspi switching specifications (high-speed mode).................................................................. 48 6.8.7 i2c switching specifications ................................ 50 6.8.8 uart switching specifications............................ 50 6.8.9 sdhc specifications ........................................... 50 6.8.10 i2s switching specifications ................................ 51 6.9 human-machine interfaces (hmi)...................................... 53 6.9.1 tsi electrical specifications ................................ 53 6.9.2 lcd electrical characteristics ............................. 54 7 dimensions ............................................................................... 55 7.1 obtaining package dimensions ......................................... 55 8 pinout ........................................................................................ 56 8.1 k40 signal multiplexing and pin assignments .................. 56 8.2 k40 pinouts ....................................................................... 60 9 revision history ........................................................................ 61 k40 sub-family data sheet data sheet, rev. 4, 3/2011. 2 preliminary freescale semiconductor, inc.
1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: pk40 and mk40. 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## m fff t pp ccc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status m = fully qualified, general market flow p = prequalification k## kinetis family k40 m flash memory type n = program flash only x = program flash and flexmemory table continues on the next page... rdering parts 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary
field description values fff program flash memory size 32 = 32 kb 64 = 64 kb 128 = 128 kb 256 = 256 kb 512 = 512 kb 1m0 = 1 mb t temperature range (?c) v = 40 to 105 c = 40 to 85 pp package identifier fm = 32 qfn (5 mm x 5 mm) ft = 48 qfn (7 mm x 7 mm) lf = 48 lqfp (7 mm x 7 mm) ex = 64 qfn (9 mm x 9 mm) lh = 64 lqfp (10 mm x 10 mm) lk = 80 lqfp (12 mm x 12 mm) mb = 81 mapbga (8 mm x 8 mm) ll = 100 lqfp (14 mm x 14 mm) mc = 121 mapbga (8 mm x 8 mm) lq = 144 lqfp (20 mm x 20 mm) md = 144 mapbga (13 mm x 13 mm) mf = 196 mapbga (15 mm x 15 mm) mj = 256 mapbga (17 mm x 17 mm) ccc maximum cpu frequency (mhz) 50 = 50 mhz 72 = 72 mhz 100 = 100 mhz 120 = 120 mhz 150 = 150 mhz n packaging type r = tape and reel (blank) = trays 2.4 example this is an example part number: mk40n512vmd100 3 terminology and guidelines 3.1 definition: operating requirement an operating requirement is a speciied value or range o values or a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useul lie o the chip erminology and guidelines ubamily ata heet ata heet ev reliminary reescale emiconductor nc
3.1.1 example this is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 3.2 definition: operating behavior an operating behavior is a speciied value or range o values or a technical characteristic that are guaranteed during operation i you meet the operating requirements and any other speciied conditions ample his is an eample o an operating behavior hich is guaranteed i you meet the accompanying operating requirements ymbol escription in a nit igital o ea pullup pulldon current einition ttribute n attribute is a speciied value or range o values or a technical characteristic that are guaranteed regardless o hether you meet the operating requirements ample his is an eample o an attribute ymbol escription in a nit nput capacitance digital pins p erminology and guidelines ubamily ata heet ata heet ev reescale emiconductor nc reliminary
3.4 definition: rating a rating is a minimum or maimum value o a technical characteristic that i eceeded may cause permanent chip ailure operating ratings apply during operation o the chip handling ratings apply hen the chip is not poered ample his is an eample o an operating rating ymbol escription in a nit core supply voltage esult o eceeding a rating easured characteristic operating rating ailures in time ppm he lielihood o permanent chip ailure increases rapidly as soon as a characteristic begins to eceed one o its operating ratings erminology and guidelines ubamily ata heet ata heet ev reliminary reescale emiconductor nc
3.6 relationship between ratings and operating requirements typical value is a speciied value or a technical characteristic that ies ithin the range o values speciied by the operating behavior iven the typical manuacturing process is representative o that characteristic during operation hen you meet the typicalvalue conditions or other speciied conditions ypical values are provided as design guidelines and are neither tested nor guaranteed ample his is an eample o an operating behavior that includes a typical value erminology and guidelines ubamily ata heet ata heet ev reescale emiconductor nc reliminary
symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 ?c 105 ?c 25 ?c 40 ?c v dd (v) i (?a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 ?c v dd 3.3 v supply voltage 3.3 v 4 ratings ratings k40 sub-family data sheet data sheet, rev. 4, 3/2011. 8 preliminary freescale semiconductor, inc.
4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature 55 150 ?c 1 t sdr solder temperature, lead-free 260 ?c 2 solder temperature, leaded 245 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/edec standard -std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . .2 moisture handling ratings symbol description min. max. nit notes msl moisture sensitivity level 1 1. determined according to ipc/edec standard -std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . . esd handling ratings symbol description min. max. nit notes hbm electrostatic discharge voltage, human body model -2000 2000 1 cdm electrostatic discharge voltage, charged-device model -500 500 2 i lat latch-up current at ambient temperature of 5c -100 100 ma 1. determined according to edec standard esd22-a11, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to edec standard esd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . . oltage and current operating ratings symbol description min. max. nit dd digital supply voltage 0. . i dd digital supply current 15 ma di digital input voltage (except reset, etal, and tal) 0. 5.5 table continues on the next page... ratings 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary
symbol description min. max. unit v aio analog, reset, extal, and xtal input voltage 0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all port pins) 25 25 ma v dda analog supply voltage v dd 0.3 v dd + 0.3 v v usb_dp usb_dp input voltage 0.3 3.63 v v usb_dm usb_dm input voltage 0.3 3.63 v vregin usb regulator input 0.3 6.0 v v bat rtc battery supply voltage 0.3 3.8 v 5 general 5.1 nonswitching electrical specifications 5.1.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd v dda v dd -to-v dda differential voltage 0.1 0.1 v v ss v ssa v ss -to-v ssa differential voltage 0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v table continues on the next page... general 0 sub-family data sheet data sheet, rev. , /2011. 10 preliminary freescale semiconductor, inc.
table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes i ic dc injection current single pin v in < v ss 0 0.2 ma 1 dc injection current total mcu limit, includes sum of all stressed pins v in < v ss 0 5 ma 1 v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file tbd v 1. all functional non-supply pins are internally clamped to v ss , and induce an injection current when v in is less than v ss . the i ic maximum operating requirement should not be exceeded. if this requirement cannot be met, the input must be current limited to the value specified. 5.1.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage tbd 1.1 tbd v v lvdh falling low-voltage detect threshold high range (lvdv=01) tbd 2.56 tbd v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) tbd tbd tbd tbd 2.70 2.80 2.90 3.00 tbd tbd tbd tbd v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) tbd 1.60 tbd v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) tbd tbd tbd tbd 1.80 1.90 2.00 2.10 tbd tbd tbd tbd v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv v bg bandgap voltage reference tbd 1.00 tbd v t lpo internal low power oscillator period factory trimmed tbd 1000 tbd s general k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 11
1. rising thresholds are falling threshold + hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage tbd 1.1 tbd v 5.1.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage high drive strength 2.7 v ? v dd ? 3.6 v, i oh = -10ma 1.71 v ? v dd ? 2.7 v, i oh = -3ma v dd 0.5 v dd 0.5 v v output high voltage low drive strength 2.7 v ? v dd ? 3.6 v, i oh = -2ma 1.71 v ? v dd ? 2.7 v, i oh = -0.6ma v dd 0.5 v dd 0.5 v v i oht output high current total for all ports 100 ma v ol output low voltage high drive strength 2.7 v ? v dd ? 3.6 v, i ol = 10ma 1.71 v ? v dd ? 2.7 v, i ol = 3ma 0.5 0.5 v v output low voltage low drive strength 2.7 v ? v dd ? 3.6 v, i ol = 2ma 1.71 v ? v dd ? 2.7 v, i ol = 0.6ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i in input leakage current (per pin) 1 a 1 i oz hi-z (off-state) leakage current (per pin) 1 a r pu internal pullup resistors 30 50 k? 2 r pd internal pulldown resistors 30 50 k? 3 1. measured at vdd=3.6v 2. measured at v dd supply voltage = v dd min and vinput = v ss 3. measured at v dd supply voltage = v dd min and vinput = v dd 5.1.4 power mode transition operating behaviors all specifications except t por , and vllsx
? cpu and system clocks = 100 mhz ? bus clock = 50 mhz ? flash clock = 25 mhz table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.8v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 run table continues on the next page... general 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary 1
table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_run run mode current all peripheral clocks disabled, code executing from flash @ 1.8v @ 3.0v 40 42 tbd tbd ma ma 2 i dd_run run mode current all peripheral clocks enabled, code executing from flash @ 1.8v @ 3.0v 55 56 tbd tbd ma ma 3 i dd_run_m ax run mode current all peripheral clocks enabled and peripherals active, code executing from flash @ 1.8v @ 3.0v 85 85 tbd tbd ma ma 4 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 35 tbd ma 2 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks disabled 15 tbd ma 5 i dd_stop stop mode current at 3.0 v 0.4 tbd ma i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 1.25 tbd ma 6 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled tbd tbd ma 7 i dd_vlpw very-low-power wait mode current at 3.0 v 1.05 tbd ma 8 i dd_vlps very-low-power stop mode current at 3.0 v 50 tbd a i dd_lls low leakage stop mode current at 3.0 v 12 tbd a i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v 128kb ram devices 8 tbd a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v 4 tbd a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v 2 tbd a i dd_vbat average current when cpu is not accessing rtc registers at 3.0 v 550 tbd na 9 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module?s specification for its supply current. 2. 100mhz core and system clock, 50mhz bus clock, and 25mhz flash clock . mcg configured for fei mode. all peripheral clocks disabled. 3. 100mhz core and system clock, 50mhz bus clock, and 25mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled, but peripherals are not in active operation. 4. 100mhz core and system clock, 50mhz bus clock, and 25mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled, and peripherals are in active operation. 5. 25mhz core and system clock, 25mhz bus clock, and 12.5mhz flash clock. mcg configured for fei mode. 6. 2 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for fast irclk mode. all peripheral clocks disabled. code executing from flash. general k40 sub-family data sheet data sheet, rev. 4, 3/2011. 14 preliminary freescale semiconductor, inc.
7. 2 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for fast irclk mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 8. 2 mhz core, system, and bus clock and 1mhz flash clock. mcg configured for fast irclk mode. all peripheral clocks disabled. 9. includes 32khz oscillator current and rtc operation. 5.1.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fei mode (39.0625 khz irc), except for 1 mhz core (fbe) ? all peripheral clocks disabled except ftfl ? lvd disabled, usb regulator disabled ? no gpios toggled ? code execution from flash figure 1. run mode supply current vs. core frequency all peripheral clocks disabled the following data was measured under these conditions: ? mcg in fei mode (39.0625 khz irc), except for 1 mhz core (fbe) general k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 15
? all peripheral clocks enabled but peripherals are not in active operation ? lvd disabled, usb regulator disabled ? no gpios toggled ? code execution from flash figure 2. run mode supply current vs. core frequency all peripheral clocks enabled 5.1.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.1550 tbd dbv 1 , 2 v re2 radiated emissions voltage, band 2 50150 tbd v re3 radiated emissions voltage, band 3 150500 tbd v re4 radiated emissions voltage, band 4 5001000 tbd v re_iec_sae iec and sae level 0.151000 tbd 2 , 3 general k40 sub-family data sheet data sheet, rev. 4, 3/2011. 16 preliminary freescale semiconductor, inc.
1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions , iec standard 1-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method , and sae standard 152-, measurement of radiated emissions from integrated circuitstem/ wideband tem (gtem) cell method . 2. dd , t a 25 c, f sc 12 mhz (crystal), f ss mhz . specified according to annex d of iec standard 1-2, measurement of radiated emissionstem cell and wideband tem cell method , and appendix d of sae standard 152-, measurement of radiated emissions from integrated circuitstem/wideband tem (gtem) cell method . 5.1. designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to http://www.freescale.com . 2. perform a keyword search for emc design. 5.1. capacitance attributes table . capacitance attributes symbol description min. max. nit c ina input capacitance: analog pins pf c ind input capacitance: digital pins pf 5.2 switching specifications 5.2.1 device clock specifications symbol description min. max. nit notes normal run mode f ss system and core clock 100 mhz f sssb system and core clock when sb in operation 20 mhz f bs bus clock 50 mhz f flash flash clock 25 mhz lpr mode f ss system and core clock 2 mhz f bs bus clock 2 mhz table continues on the next page... general 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary 1
symbol description min. max. unit notes f flash flash clock 1 mhz 5.2.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, can, cmt, and i 2 c signals. symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 16 ns 2 external reset pulse width (digital glitch filter disabled) tbd mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) slew disabled slew enabled 12 36 ns ns 3 port rise and fall time (low drive strength) slew disabled slew enabled 32 36 ns ns 4 1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 3. 75pf load 4. 15pf load 5.3 thermal specifications 5.3.1 thermal operating requirements table 9. thermal operating requirements symbol description min. max. unit t j die junction temperature 40 125 ?c t a ambient temperature 40 ?c general k40 sub-family data sheet data sheet, rev. 4, 3/2011. 18 preliminary freescale semiconductor, inc.
5.3.2 thermal attributes board type symbol description 121 mapbga unit notes single-layer (1s) r integrated circuits thermal test method environmental conditionsnatural convection (still air) , or eia/edec standard esd51-, integrated circuit thermal test method environmental conditionsforced convection (moving air) . peripheral operating reuirements and behaviors all digital i/ switching characteristics assume: 1. output pins have c l 0pf loads, are configured for fast slew rate (prtxpcrnsre0), and are configured for high drive strength (prtxpcrndse1) 2. input pins have their passive filter disabled (prtxpcrnpfe0) .1 core modules .1.1 debug trace timing specifications table 10. debug trace operating behaviors symbol description min. max. nit t cyc clock period freuency dependent mhz table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary 1
table 10. debug trace operating behaviors (continued) symbol description min. max. unit t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 3 ns t h data hold 2 ns figure 3. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 4. trace data specifications 6.1.2 jtag electricals table 11. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation boundary scan jtag and cjtag serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. 20 preliminary freescale semiconductor, inc.
table 11. jtag limited voltage range electricals (continued) symbol description min. max. unit j3 tclk clock pulse width boundary scan jtag and cjtag serial wire debug 50 20 10 ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 0 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 17 ns j12 tclk low to tdo high-z 17 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 12. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation boundary scan jtag and cjtag serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width boundary scan jtag and cjtag serial wire debug 50 25 12.5 ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 0 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary 21
table 12. jtag full voltage range electricals (continued) symbol description min. max. unit j10 tms, tdi input data hold time after tclk rise 1.4 ns j11 tclk low to tdo data valid 22.1 ns j12 tclk low to tdo high-z 22.1 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns j2 j3 j3 j4 j4 tclk (input) figure 5. test clock input timing j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 6. boundary scan (jtag) timing peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. 22 preliminary freescale semiconductor, inc.
j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 7. test access port timing j14 j13 tclk trst figure 8. trst timing 6.2 system modules there are no specifications necessary for the devices system modules. 6.3 clock modules peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 23
6.3.1 mcg specifications table 13. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25?c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz i ints internal reference (slow clock) current tbd a t irefsts internal reference (slow clock) startup time tbd 4 s table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. 2 preliminary freescale semiconductor, inc.
table 13. mcg specifications (continued) symbol description min. typ. max. unit notes f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 4 , 5 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter tbd tbd ps 6 j acc_fll fll accumulated jitter of dco output over a 1s time window tbd tbd ps 6 t fll_acquire fll target frequency acquisition time 1 ms 7 pll f vco vco operating frequency 48.0 100 mhz i pll pll operating current pll @ 96 mhz (f osc_hi_1 =8mhz, f pll_ref =2mhz, vdiv multiplier=48) 950 a 8 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter 400 ps 9 , 10 j acc_pll pll accumulated jitter over 1s window tbd ps 9 , 10 d lock lock entry frequency tolerance ? 1.49 ? 2.98 % d unl lock exit frequency tolerance ? 4.47 ? 5.97 % t pll_lock lock detector detection time 0.15 + 1075(1/ f pll_ref ) ms 11 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation (
6.3.2 oscillator electrical specifications this section provides the electrical characteristics of the module. 6.3.2.1 oscillator dc electrical specifications table 14. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) 32 khz 4 mhz 8 mhz 16 mhz 24 mhz 32 mhz 500 200 300 700 1.2 1.5 na a a a ma ma 1 i ddosc supply current high gain mode (hgo=1) 32 khz 4 mhz 8 mhz 16 mhz 24 mhz 32 mhz 25 400 800 1.5 3 4 a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m? 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m? feedback resistor high-frequency, low-power mode (hgo=0) m? feedback resistor high-frequency, high-gain mode (hgo=1) 1 m? table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. 2 preliminary freescale semiconductor, inc.
table 14. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes r s series resistor low-frequency, low-power mode (hgo=0) k? series resistor low-frequency, high-gain mode (hgo=1) 200 k? series resistor high-frequency, low-power mode (hgo=0) k? series resistor high-frequency, high-gain mode (hgo=1) 0 k? v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 ?c 2. see crystal or resonator manufacturer?s recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 oscillator frequency specifications table 15. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary 2
table 15. oscillator frequency specifications (continued) symbol description min. typ. max. unit notes t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) tbd ms 2 , 3 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 800 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 4 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 3 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll 2. proper pc board layout procedures must be followed to achieve specifications. 3. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 6.3.3 32khz oscillator electrical characteristics this section describes the module electrical characteristics. 6.3.3.1 32khz oscillator dc electrical specifications table 16. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m? c para parasitical capacitance of extal32 and xtal32 2.5 pf c load internal load capacitance (programmable) 15 pf v pp peak-to-peak amplitude of oscillation 0.6 v 6.3.3.2 32khz oscillator frequency specifications table 17. 32khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32 khz t start crystal start-up time 1000 ms 1 1. proper pc board layout procedures must be followed to achieve specifications. 6.4 memories and memory interfaces peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. 28 preliminary freescale semiconductor, inc.
6.4.1 flash (ftfl) electrical specifications this section describes the electrical characteristics of the ftfl module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 18. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 20 tbd s t hversscr sector erase high-voltage time 20 100 ms 1 t hversblk256k erase block high-voltage time for 256 kb 160 800 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing specifications commands table 19. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk256k read 1s block execution time 256 kb data flash 1.4 ms t rd1sec2k read 1s section execution time (flash sector) 40 s 1 t pgmchk program check execution time 35 s 1 t rdrsrc read resource execution time 35 s 1 t pgm4 program longword execution time 50 tbd s t ersblk256k erase flash block execution time 256 kb data flash 160 800 ms 2 t ersscr erase flash sector execution time 20 100 ms 2 t pgmsec512 t pgmsec1k t pgmsec2k program section execution time 512 b flash 1 kb flash 2 kb flash tbd tbd tbd tbd tbd tbd ms ms ms t rd1all read 1s all blocks execution time 2.8 ms t rdonce read once execution time 35 s 1 t pgmonce program once execution time 50 tbd s table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary 2
table 19. flash command timing specifications (continued) symbol description min. typ. max. unit notes t ersall erase all blocks execution time 320 1600 ms 2 t vfykey verify backdoor access key execution time 35 s 1 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 6.4.1.3 flash (ftfl) current and power specfications table 20. flash (ftfl) current and power specfications symbol description typ. unit i dd_pgm worst case programming current in program flash 10 ma 6.4.1.4 reliability specifications table 21. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 tbd years 2 t nvmretp1k data retention after up to 1 k cycles 10 tbd years 2 t nvmretp100 data retention after up to 100 cycles 15 tbd years 2 n nvmcycp cycling endurance 10 k tbd cycles 3 1. typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to 25?c. for additional information on how freescale defines typical data retention, please refer to engineering bulletin eb618. 2. data retention is based on t javg = 55?c (temperature profile over the lifetime of the application). 3. cycling endurance represents number of program/erase cycles at -40?c ? t j ? 125?c. 6.4.2 ezport switching specifications table 22. ezport switching specifications num description min. max. unit operating voltage 2.7 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. 0 preliminary freescale semiconductor, inc.
table 22. ezport switching specifications (continued) num description min. max. unit ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid (setup) 12 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 9. ezport timing diagram 6.5 security and integrity modules there are no specifications necessary for the devices security and integrity modules. 6.6 analog 6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 23 and table 24 are achievable on the differential pins adcx_dp0, adcx_dm0, adcx_dp1, adcx_dm1, adcx_dp3, and adcx_dp3. peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 31
the adcx_dp2 and adcx_dm2 adc inputs are used as the pga inputs and are not direct device pins. accuracy specifications for these pins are defined in table 25 and table 26 . all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 23. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. 2 preliminary freescale semiconductor, inc.
table 23. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate 16 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50mhz 37.037 361.402 ksps 7 1. typical values assume v dda = 3.0 v, temp = 25?c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. the analog source resistance should be kept as low as possible in order to achieve the best results. the results in this datasheet were derived from a system which has <8 ? analog source resistance. the r as / c as time constant should be kept to <1ns. 4. in order to use the maximum adc conversion clock frequency adhsc bit should be set and the adlpc should be clear. 5. in order to use the maximum adc conversion clock frequency adhsc bit should be set and the adlpc should be clear. 6. for guidelines and examples of conversion rate calculation please download the adc calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 7. for guidelines and examples of conversion rate calculation please download the adc calculator tool http:// cache.freescale.com/files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 r as v as c as z as v adin z adin r adin r adin r adin r adin c adin input pin input pin input pin input pin
6.6.1.2 16-bit adc electrical characteristics table 24. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source adlpc=1, adhsc=0 adlpc=1, adhsc=1 adlpc=0, adhsc=0 adlpc=0, adhsc=1 2.4 4.0 5.2 6.2 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times conversion time the adc calculator tool can be used to determine adc conversion times for different adc configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/ converters/adc_calculator_cnv.zip?fpsp=1 tue total unadjusted error ?13 bit modes <12 bit modes ?0.8 ?0.5 ?tbd ?1 lsb 4 adc conversion clock <12mhz, max hardware averaging (avge = %1, avgs = %11) dnl differential non- linearity ?13 bit modes <12 bit modes ?0.7 ?0.2 ?tbd ?0.5 lsb 4 adc conversion clock <12mhz, max hardware averaging (avge = %1, avgs = %11) inl integral non- linearity ?13 bit modes <12 bit modes ?1.0 ?0.5 ?tbd ?tbd lsb 4 max averaging e fs full-scale error ?13 bit modes <12 bit modes ?0.4 ?1.0 ?tbd ?tbd lsb 4 v adin = v dda e q quantization error 16 bit modes ?13 bit modes -1 to 0 ?0.5 lsb 4 table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. preliminary freescale semiconductor, inc.
table 24. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes enob effective number of bits 16 bit differential mode avg=32 avg=1 16 bit single-ended mode avg=32 avg=1 tbd tbd tbd tbd 13.6 13.2 tbd tbd tbd tbd tbd tbd bits bits bits bits 5 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16 bit differential mode avg=32 16 bit single-ended mode avg=32 -94 tbd tbd tbd db db 5 sfdr spurious free dynamic range 16 bit differential mode avg=32 16 bit single-ended mode avg=32 tbd tbd 95 tbd db db 5 e il input leakage error i in r as mv i in = leakage current (refer to the mcu?s voltage and current operating ratings) temp sensor slope 40?c to 25?c 25?c to 105?c tbd tbd mv/?c mv/?c v temp25 temp sensor voltage 25?c tbd mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25?c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit should be set, the hsc bit should be clear with 1mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. input data is 1 khz sine wave. figure tbd figure 11. typical tue vs. adc conversion rate 12-bit single-ended mode peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 35
figure tbd figure 12. typical enob vs. averaging for 16-bit differential and 16-bit single-ended modes 6.6.1.3 16-bit adc with pga operating conditions table 25. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v refpga pga ref voltage vrefout vrefout vrefout v 2 , 3 v adin input voltage v ssa v dda v v cm input common mode range v ssa v dda v r pgad differntial input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 128 64 32 k? in+ to in- 4 r as analog source resistance 100 ? 5 t s adc sampling time 1.25 s 6 1. typical values assume v dda = 3.0 v, temp = 25?c, f adck = 6 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. adc must be configured to use the internal voltage reference (vrefout) 3. pga reference connected to the vrefout pin. if the user wishes to drive vrefout with a voltage other than the output of the vref module, the vref module must be disabled. 4. for single ended configurations the input impedence of the driven input is 1/2. 5. the analog source resistance (r as ), external to mcu, should be kept as minimum as possible. increased r as causes drop in pga gain without affecting other performances. this is not dependent on adc clock frequency. 6. the minimum sampling time is dependent on input signal frequency and adc mode of operation. a minimum of 1.25s time should be allowed for f in =4 khz at 16-bit differential mode. recommended adc setting is: adlsmp=1, adlsts=2 at 8 mhz adc clock. 6.6.1.4 16-bit adc with pga characteristics table 26. 16-bit adc with pga characteristics symbol description conditions min. typ. 1 max. unit notes i dda_pga supply current 590 tbd a i dc_pga input dc current a 2 i ilkg input leakage current pga disabled tbd tbd a 3 table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. preliminary freescale semiconductor, inc.
table 26. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes g gain 4 pgag=0 pgag=1 pgag=2 pgag=3 pgag=4 pgag=5 pgag=6 tbd tbd tbd tbd tbd tbd tbd 0.98 1.99 3.97 7.95 15.8 31.4 61.2 tbd tbd tbd tbd tbd tbd tbd r as < 100 table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary
table 26. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes thd total harmonic distortion gain=1 gain=64 tbd tbd 89.4 90.0 db db 16-bit differential mode, average=32, f in =500hz sfdr spurious free dynamic range gain=1 gain=64 tbd tbd 90.9 77.0 db db 16-bit differential mode, average=32, f in =500hz enob effective number of bits gain=1, average=4 gain=1, average=8 gain=64, average=4 gain=64, average=8 gain=1, average=32 gain=2, average=32 gain=4, average=32 gain=8, average=32 gain=16, average=32 gain=32, average=32 gain=64, average=32 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 12.3 12.7 8.4 8.7 13.3 13.1 12.5 11.8 11.1 10.2 9.3 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode, f in =500hz sinad signal-to-noise plus distortion ratio see enob 6.02 enob + 1.76 db 1. typical values assume v dda =3.0v, temp=25?c, f adck =6mhz unless otherwise stated. 2. between in+ and in-. the pga draws a dc current from the input terminals. the magnitude of the dc current is a strong function if input common mode voltage (v cm ) and the pga gain. 3. this is the input leakage current of the module in addition to the pad leakage current. 4. gain = 2 pgag 5. when the pga gain is changed, it takes some time to settle the output for the adc to work properly. during a gain switching, a few adc outputs should be discarded (minimum two data samples, may be more depending on adc sampling rate and time of the switching). 6. limit the input signal swing so that the pga does not saturate during operation. input signal swing is dependent on the pga reference voltage and gain setting. 6.6.2 cmp and 6-bit dac electrical specifications table 27. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. preliminary freescale semiconductor, inc.
table 27. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 cr0[hystctr] = 00 cr0[hystctr] = 01 cr0[hystctr] = 10 cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 120 250 600 ns analog comparator initialization delay 2 tbd ns i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity 0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity 0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 39
0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 13. typical hysteresis vs. vin level (vdd=3.3v, pmode=0) peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. 40 preliminary freescale semiconductor, inc.
0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 14. typical hysteresis vs. vin level (vdd=3.3v, pmode=1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 28. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 t a temperature 40 105 ?c c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be vdda or the voltage output of the vref module (vrefo) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 41
6.6.3.2 12-bit dac operating behaviors table 29. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_daclp supply current low-power mode 150 a i dda_dach p supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low- power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high- power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode 5 s 1 t ccdachp code-to-code settling time (0xbf8 to 0xc08) high-speed mode 1 tbd s 1 v dacoutl dac output voltage range low high-speed mode, no load, dac set to 0x000 100 tbd mv v dacouth dac output voltage range high high-speed mode, no load, dac set to 0xfff v dacr 100 v dacr mv inl integral non-linearity error high speed mode ?8 lsb 2 dnl differential non-linearity error v dacr > 2 v ?1 lsb 3 dnl differential non-linearity error v dacr = vrefo (1.15 v) ?1 lsb 4 v offset offset error ?0.4 ?0.8 %fsr 5 e g gain error ?0.1 ?0.6 %fsr 5 psrr power supply rejection ratio, v dda > = 2.4 v 60 90 db t co temperature coefficient offset voltage tbd v/c t ge temperature coefficient gain error tbd ppm of fsr/c a c offset aging coefficient tbd v/yr rop output resistance load = 3 k? 250 ? sr slew rate -80h
5. calculated by a best fit curve from v ss +100 mv to vref100 mv figure 15. typical inl error vs. digital code peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 43
figure 16. offset at half scale vs. temperature 6.6.4 voltage reference electrical specifications table 30. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature 40 105 ?c c l output load capacitance 100 nf table 31. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c tbd 1.2 tbd v table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. preliminary freescale semiconductor, inc.
table 31. vref full-range operating behaviors (continued) symbol description min. typ. max. unit notes v out voltage reference output with factory trim tbd tbd v v out voltage reference output user trim 1.198 1.202 v v step voltage reference trim step 0.5 mv v drift temperature drift (vmax -vmin across the full temperature range) 20 mv see figure 17 ac aging coefficient tbd ppm/year i bg bandgap only (mode_lv = 00) current tbd a i tr tight-regulation buffer (mode_lv =10) current 1.1 ma load regulation (mode_lv = 10) current = ?1.0ma tbd v t stup buffer startup time 100 s dc line regulation (power supply rejection) tbd mv 60 tbd db table 32. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 ?c table 33. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim tbd tbd v tbd figure 17. typical output vs.temperature tbd figure 18. typical output vs. vdd 6.7 timers see general switching specifications . 6.8 communication interfaces peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 45
6.8.1 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. 6.8.2 usb dcd electrical specifications table 34. usb dcd electrical specifications symbol description min. typ. max. unit v dp_src usb_dp source voltage (up to 250 a) tbd tbd tbd v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 a i dm_sink usb_dm sink current 50 100 150 a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k? v dat_ref data detect voltage 0.25 tbd 0.4 v 6.8.3 usb vreg electrical specifications table 35. usb vreg electrical specifications symbol description min. typ. max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 120 tbd a i ddstby quiescent current standby mode, load current equal zero 1 tbd a i ddoff quiescent current shutdown mode vregin = 5.0 v and temperature=25c across operating voltage and temperature 500 tbd na a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v run mode standby mode 3 2.5 3.3 2.8 3.6 3.6 v v table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. preliminary freescale semiconductor, inc.
table 35. usb vreg electrical specifications (continued) symbol description min. typ. max. unit notes v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.3 3.6 v 1 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m? i lim current limitation threshold 185 290 395 ma 1. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 6.8.4 can switching specifications see general switching specifications . 6.8.5 dspi switching specifications (low-speed mode) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 36. master mode dspi timing (low-speed mode) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 12.5 mhz ds1 dspi_sck output cycle time 4 x t bclk ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n to dspisc output valid (t sc /2) - ns ds dspisc to dspipcs n output hold (t sc /2) - ns ds5 dspisc to dspist valid 10 ns ds dspisc to dspist invalid -2 ns ds dspisin to dspisc input setup 15 ns ds dspisc to dspisin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum freuency of operation is reduced. peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary
ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 19. dspi classic spi timing master mode table 37. slave mode dspi timing (low-speed mode) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 6.25 mhz ds9 dspi_sck input cycle time 8 x t bclk ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 20 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 5 ns ds14 dspi_sck to dsip_sin input hold 15 ns ds15 dspi_ss active to dspi_sout driven 15 ns ds16 dspi_ss inactive to dspi_sout not driven 15 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 20. dspi classic spi timing slave mode peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. 48 preliminary freescale semiconductor, inc.
6.8.6 dspi switching specifications (high-speed mode) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 38. master mode dspi timing (high-speed mode) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 25 mhz ds1 dspi_sck output cycle time 2 x t bclk ns ds2 dspi_sck output high/low time (t sck /2) 2 (t sck /2) + 2 ns ds3 dspi_pcs n to dspisc output valid (t sc /2) 2 ns ds dspisc to dspipcs n output hold (t sc /2) 2 ns ds5 dspisc to dspist valid .5 ns ds dspisc to dspist invalid 2 ns ds dspisin to dspisc input setup tbd ns ds dspisc to dspisin input hold 0 ns ds ds ds1 ds2 ds ds first data last data ds5 first data data last data ds data dspipcsn dspisc (cpl0) dspisin dspist figure 21. dspi classic spi timing master mode table . slave mode dspi timing (high-speed mode) num description min. max. nit perating voltage 2. . freuency of operation 12.5 mhz ds dspisc input cycle time x t bcl ns ds10 dspisc input high/low time (t sc /2) 2 (t sc /2 2 ns table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary
table 39. slave mode dspi timing (high-speed mode) (continued) num description min. max. unit ds11 dspi_sck to dspi_sout valid tbd ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dsip_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 22. dspi classic spi timing slave mode 6.8.7 i 2 c switching specifications see general switching specifications . 6.8.8 uart switching specifications see general switching specifications . peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. 50 preliminary freescale semiconductor, inc.
6.8.9 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 40. sdhc switching specifications num symbol description min. max. unit operating voltage 2.7 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed) 0 25 mhz fpp clock frequency (mmc full speed) 0 20 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 6.5 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t thl sdhc input setup time 5 ns sd8 t thl sdhc input hold time 0 ns sd2sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 23. sdhc timing peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 51
6.8.10 i 2 s switching specifications this section provides the ac timings for the i 2 s in master (clocks driven) and slave modes (clocks input). all timings are given for non-inverted serial clock polarity (tcr[tsckp] = 0, rcr[rsckp] = 0) and a non-inverted frame sync (tcr[tfsi] = 0, rcr[rfsi] = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (i2s_bclk) and/or the frame sync (i2s_fs) shown in the figures below. table 41. i 2 s master mode timing num description min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 2 x t sys ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_bclk cycle time 5 x t sys ns s4 i2s_bclk pulse width high/low 45% 55% bclk period s5 i2s_bclk to i2s_fs output valid 15 ns s6 i2s_bclk to i2s_fs output invalid -2.5 ns s7 i2s_bclk to i2s_txd valid 15 ns s8 i2s_bclk to i2s_txd invalid -3 ns s9 i2s_rxd/i2s_fs input setup before i2s_bclk 20 ns s10 i2s_rxd/i2s_fs input hold after i2s_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_bclk (output) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd figure 24. i 2 s timing master mode peripheral operating requirements and behaviors k40 sub-family data sheet data sheet, rev. 4, 3/2011. 52 preliminary freescale semiconductor, inc.
table 42. i 2 s slave mode timing num description min. max. unit operating voltage 2.7 3.6 v s11 i2s_bclk cycle time (input) 8 x t sys ns s12 i2s_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_fs input setup before i2s_bclk 10 ns s14 i2s_fs input hold after i2s_bclk 3 ns s15 i2s_bclk to i2s_txd/i2s_fs output valid 20 ns s16 i2s_bclk to i2s_txd/i2s_fs output invalid 0 ns s17 i2s_rxd setup before i2s_bclk 10 ns s18 i2s_rxd hold after i2s_bclk 2 ns s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_bclk (input) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd figure 25. i 2 s timing slave modes 6.9 human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 43. tsi electrical specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 5.5 tbd mhz f elemax electrode oscillator frequency 0.5 tbd mhz table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. freescale semiconductor, inc. preliminary 5
table 43. tsi electrical specifications (continued) symbol description min. typ. max. unit notes c ref internal reference capacitor tbd 1 tbd pf v delta oscillator delta voltage tbd 600 tbd mv i ref reference oscillator current source base current tbd 1 tbd a 2 i ele electrode oscillator current source base current tbd 1 tbd a 2 pres5 electrode capacitance measurement precision tbd tbd % 3 pres20 electrode capacitance measurement precision tbd tbd % 4 pres100 electrode capacitance measurement precision tbd tbd % 5 maxsens2 0 maximum sensitivity @ 20 pf electrode 0.003 0.25 ff/count 6 maxsens maximum sensitivity 0.003 ff/count 7 res resolution 16 bits t con20 response time @ 20 pf 8 15 25 s 8 i tsi_run current added in run mode tbd a i tsi_lp low power mode current adder 1 tbd a 1. the tsi module is functional with capacitance values outside this range. however, optimal performance is not guaranteed. 2. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current. 3. measured with a 5 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 8; iext = 16. 4. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 2; iext = 16. 5. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 16, nscn = 3; iext = 16. 6. measured with a 20 pf electrode, reference oscillator frequency of ~5 mhz (i ref = 5 table continues on the next page... peripheral operating reuirements and behaviors 0 sub-family data sheet data sheet, rev. , /2011. 5 preliminary freescale semiconductor, inc.
table 44. lcd electricals (continued) symbol description min. typ. max. unit notes v ireg ripple hrefsel = 0 hrefsel = 1 30 50 mv mv i vireg v ireg current adder rven = 1 1 a 3 i rbias rbias current adder hrefsel = 0 hrefsel = 1 10 1 a a 3 r rbias rbias resistor values ladj = 00 or 01 low load (lcd glass capacitance ? 2000 pf) ladj = 10 or 11 high load (lcd glass capacitance ? 8000 pf) 0.28 2.98 m? m? vll2 vll2 voltage hrefsel = 0 hrefsel = 1 2.0 5% 3.3 5% 2.0 3.3 v v vll3 vll3 voltage hrefsel = 0 hrefsel = 1 3.0 5% 5 5% 3.0 5 v v 1. the actual value used could vary with tolerance. 2. v ireg maximum should never be externally driven to any level other than v dd - 0.15 v 3. 2000 pf load lcd, 32 hz frame frequency 7 dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawing?s document number: if you want the drawing for this package then use this document number 121-pin mapbga tbd dimensions k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 55
8 pinout 8.1 k40 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx sdhc0_d1 i2c1_sda pte1 adc1_se5a adc1_se5a pte1 spi1_sout uart1_rx sdhc0_d0 i2c1_scl pte2 adc1_se6a adc1_se6a pte2 spi1_sck uart1_cts _b sdhc0_dcl k pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_rts _b sdhc0_cm d pte4 disabled pte4 spi1_pcs0 uart3_tx sdhc0_d3 pte5 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 pte6 disabled pte6 spi1_pcs3 uart3_cts _b i2s0_mclk i2s0_clkin vdd vdd vdd vss vss vss usb0_dp usb0_dp usb0_dp usb0_dm usb0_dm usb0_dm vout33 vout33 vout33 vregin vregin vregin adc0_dp1 adc0_dp1 adc0_dp1 adc0_dm1 adc0_dm1 adc0_dm1 adc1_dp1 adc1_dp1 adc1_dp1 adc1_dm1 adc1_dm1 adc1_dm1 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 vdda vdda vdda pinout k40 sub-family data sheet data sheet, rev. 4, 3/2011. 56 preliminary freescale semiconductor, inc.
121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport vrefh vrefh vrefh vrefl vrefl vrefl vssa vssa vssa vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 dac0_out/ cmp1_in3/ adc0_se23 dac0_out dac0_out/ cmp1_in3/ adc0_se23 dac1_out/ cmp2_in3/ adc1_se23 dac1_out dac1_out/ cmp2_in3/ adc1_se23 xtal32 xtal32 xtal32 extal32 extal32 extal32 vbat vbat vbat pte24 adc0_se17 adc0_se17 pte24 can1_tx uart4_tx ewm_out_ b pte25 adc0_se18 adc0_se18 pte25 can1_rx uart4_rx ewm_in pte26 disabled pte26 uart4_cts _b rtc_clko ut usb_clkin pta0 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_cts _b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di pta2 jtag_tdo/ trace_sw o/ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_sw o ezp_do pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rts _b ftm0_ch0 jtag_tms/ swd_dio pta4 nmi_b/ ezp_cs_b tsi0_ch5 pta4 ftm0_ch1 nmi_b ezp_cs_b pta5 disabled pta5 ftm0_ch2 cmp2_out i2s0_rx_bc lk jtag_trst pta10 disabled pta10 ftm2_ch0 ftm2_qd_p ha trace_d0 pta11 disabled pta11 ftm2_ch1 ftm2_qd_p hb pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 i2s0_txd ftm1_qd_p ha pta13 cmp2_in1 cmp2_in1 pta13 can0_rx ftm1_ch1 i2s0_tx_fs ftm1_qd_p hb pta14 disabled pta14 spi0_pcs0 uart0_tx i2s0_tx_bc lk pta15 disabled pta15 spi0_sck uart0_rx i2s0_rxd pinout k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 57
121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport pta16 disabled pta16 spi0_sout uart0_cts _b i2s0_rx_fs pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_rts _b i2s0_mclk i2s0_clkin vdd vdd vdd vss vss vss pta18 extal extal pta18 ftm0_flt2 ftm_clkin 0 pta19 xtal xtal pta19 ftm1_flt0 ftm_clkin 1 lpt0_alt1 reset_b reset_b reset_b pta24 disabled pta24 pta25 disabled pta25 pta26 disabled pta26 pta27 disabled pta27 pta28 disabled pta28 pta29 disabled pta29 ptb0 lcd_p0/ adc0_se8/ adc1_se8/ tsi0_ch0 lcd_p0/ adc0_se8/ adc1_se8/ tsi0_ch0 ptb0 i2c0_scl ftm1_ch0 ftm1_qd_p ha lcd_p0 ptb1 lcd_p1/ adc0_se9/ adc1_se9/ tsi0_ch6 lcd_p1/ adc0_se9/ adc1_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 ftm1_qd_p hb lcd_p1 ptb2 lcd_p2/ adc0_se12/ tsi0_ch7 lcd_p2/ adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_rts _b ftm0_flt3 lcd_p2 ptb3 lcd_p3/ adc0_se13/ tsi0_ch8 lcd_p3/ adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_cts _b ftm0_flt0 lcd_p3 ptb6 lcd_p6/ adc1_se12 lcd_p6/ adc1_se12 ptb6 lcd_p6 ptb7 lcd_p7/ adc1_se13 lcd_p7/ adc1_se13 ptb7 lcd_p7 ptb8 lcd_p8 lcd_p8 ptb8 uart3_rts _b lcd_p8 ptb9 lcd_p9 lcd_p9 ptb9 spi1_pcs1 uart3_cts _b lcd_p9 ptb10 lcd_p10/ adc1_se14 lcd_p10/ adc1_se14 ptb10 spi1_pcs0 uart3_rx ftm0_flt1 lcd_p10 ptb11 lcd_p11/ adc1_se15 lcd_p11/ adc1_se15 ptb11 spi1_sck uart3_tx ftm0_flt2 lcd_p11 ptb16 lcd_p12/ tsi0_ch9 lcd_p12/ tsi0_ch9 ptb16 spi1_sout uart0_rx ewm_in lcd_p12 ptb17 lcd_p13/ tsi0_ch10 lcd_p13/ tsi0_ch10 ptb17 spi1_sin uart0_tx ewm_out_ b lcd_p13 pinout k40 sub-family data sheet data sheet, rev. 4, 3/2011. 58 preliminary freescale semiconductor, inc.
121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport ptb18 lcd_p14/ tsi0_ch11 lcd_p14/ tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_bc lk ftm2_qd_p ha lcd_p14 ptb19 lcd_p15/ tsi0_ch12 lcd_p15/ tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_fs ftm2_qd_p hb lcd_p15 ptb20 lcd_p16 lcd_p16 ptb20 spi2_pcs0 cmp0_out lcd_p16 ptb21 lcd_p17 lcd_p17 ptb21 spi2_sck cmp1_out lcd_p17 ptb22 lcd_p18 lcd_p18 ptb22 spi2_sout cmp2_out lcd_p18 ptb23 lcd_p19 lcd_p19 ptb23 spi2_sin spi0_pcs5 lcd_p19 ptc0 lcd_p20/ adc0_se14/ tsi0_ch13 lcd_p20/ adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_extr g i2s0_txd lcd_p20 ptc1 lcd_p21/ adc0_se15/ tsi0_ch14 lcd_p21/ adc0_se15/ tsi0_ch14 ptc1 spi0_pcs3 uart1_rts _b ftm0_ch0 lcd_p21 ptc2 lcd_p22/ adc0_se4b/ cmp1_in0/ tsi0_ch15 lcd_p22/ adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_cts _b ftm0_ch1 lcd_p22 ptc3 lcd_p23/ cmp1_in1 lcd_p23/ cmp1_in1 ptc3 spi0_pcs1 uart1_rx ftm0_ch2 lcd_p23 vss vss vss vll3 vll3 vll3 vll2 vll2 vll2 vll1 vll1 vll1 vcap2 vcap2 vcap2 vcap1 vcap1 vcap1 ptc4 lcd_p24 lcd_p24 ptc4 spi0_pcs0 uart1_tx ftm0_ch3 cmp1_out lcd_p24 ptc5 lcd_p25 lcd_p25 ptc5 spi0_sck lpt0_alt2 cmp0_out lcd_p25 ptc6 lcd_p26/ cmp0_in0 lcd_p26/ cmp0_in0 ptc6 spi0_sout pdb0_extr g lcd_p26 ptc7 lcd_p27/ cmp0_in1 lcd_p27/ cmp0_in1 ptc7 spi0_sin lcd_p27 ptc8 lcd_p28/ adc1_se4b/ cmp0_in2 lcd_p28/ adc1_se4b/ cmp0_in2 ptc8 i2s0_mclk i2s0_clkin lcd_p28 ptc9 lcd_p29/ adc1_se5b/ cmp0_in3 lcd_p29/ adc1_se5b/ cmp0_in3 ptc9 i2s0_rx_bc lk ftm2_flt0 lcd_p29 ptc10 lcd_p30/ adc1_se6b/ cmp0_in4 lcd_p30/ adc1_se6b/ cmp0_in4 ptc10 i2c1_scl i2s0_rx_fs lcd_p30 ptc11 lcd_p31/ adc1_se7b lcd_p31/ adc1_se7b ptc11 i2c1_sda i2s0_rxd lcd_p31 ptc12 lcd_p32 lcd_p32 ptc12 uart4_rts _b lcd_p32 pinout k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 59
121 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport ptc13 lcd_p33 lcd_p33 ptc13 uart4_cts _b lcd_p33 ptc14 lcd_p34 lcd_p34 ptc14 uart4_rx lcd_p34 ptc15 lcd_p35 lcd_p35 ptc15 uart4_tx lcd_p35 ptc16 lcd_p36 lcd_p36 ptc16 can1_rx uart3_rx lcd_p36 ptc17 lcd_p37 lcd_p37 ptc17 can1_tx uart3_tx lcd_p37 ptc18 lcd_p38 lcd_p38 ptc18 uart3_rts _b lcd_p38 ptc19 lcd_p39 lcd_p39 ptc19 uart3_cts _b lcd_p39 ptd0 lcd_p40 lcd_p40 ptd0 spi0_pcs0 uart2_rts _b lcd_p40 ptd1 lcd_p41/ adc0_se5b lcd_p41/ adc0_se5b ptd1 spi0_sck uart2_cts _b lcd_p41 ptd2 lcd_p42 lcd_p42 ptd2 spi0_sout uart2_rx lcd_p42 ptd3 lcd_p43 lcd_p43 ptd3 spi0_sin uart2_tx lcd_p43 ptd4 lcd_p44 lcd_p44 ptd4 spi0_pcs1 uart0_rts _b ftm0_ch4 ewm_in lcd_p44 ptd5 lcd_p45/ adc0_se6b lcd_p45/ adc0_se6b ptd5 spi0_pcs2 uart0_cts _b ftm0_ch5 ewm_out_ b lcd_p45 ptd6 lcd_p46/ adc0_se7b lcd_p46/ adc0_se7b ptd6 spi0_pcs3 uart0_rx ftm0_ch6 ftm0_flt0 lcd_p46 vss vss vss vdd vdd vdd ptd7 lcd_p47 lcd_p47 ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 lcd_p47 ptd8 disabled ptd8 i2c0_scl ptd9 disabled ptd9 i2c0_sda ptd10 disabled ptd10 ptd11 disabled ptd11 spi2_pcs0 sdhc0_clk in ptd12 disabled ptd12 spi2_sck sdhc0_d4 ptd13 disabled ptd13 spi2_sout sdhc0_d5 ptd14 disabled ptd14 spi2_sin sdhc0_d6 ptd15 disabled ptd15 spi2_pcs1 sdhc0_d7 8.2 k40 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout k40 sub-family data sheet data sheet, rev. 4, 3/2011. 60 preliminary freescale semiconductor, inc.
note the 121 mapbga ballmap assignments are currently being developed. 9 revision history the following table provides a revision history for this document. table 45. revision history rev. no. date substantial changes 1 11/2010 initial public revision 2 3/2011 many updates throughout 3 3/2011 added sections that were inadvertently removed in previous revision 4 3/2011 reworded i ic footnote in "voltage and current operating requirements" table. added paragraph to "peripheral operating requirements and behaviors" section. added "jtag full voltage range electricals" table to the "jtag electricals" section. revision history k40 sub-family data sheet data sheet, rev. 4, 3/2011. freescale semiconductor, inc. preliminary 61
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